1. Technical Field
Embodiments relate to a three-dimensional (3D) nonvolatile memory device, and more particularly, to a 3D nonvolatile memory device with stacked word lines which are integrally formed, spaced apart by a given distance, and elongated over adjacent cell regions.
2. Related Art
Nonvolatile semiconductor memory devices are memory devices in which stored data is retained even when power is interrupted. Currently, various nonvolatile memory devices such as, flash memory devices and the like have been widely used.
The flash memory devices are characterized by data programming and erasing being electrically performed. The flash memory device includes a plurality of blocks having memory cells, and each of the blocks includes a plurality of pages. In particular, erasing data, which is stored in the memory cells, is performed on a block.
Currently, as a degree of integration in 2D nonvolatile memory devices in which memory cells are two-dimensionally formed on a semiconductor substrate reaches its limit, 3D nonvolatile memory devices having a channel layer which is vertically protruding from a semiconductor substrate have been proposed.
3D nonvolatile memory devices are typically classified into devices having a line type channel layer and devices having a U-shaped channel layer. In the 3D nonvolatile memory devices having the line type channel layer, bit lines and source lines are arranged over and under stacked memory cells. In the 3D nonvolatile memory devices having the U-shaped channel layer, both the bit lines and source lines are arranged over the stacked memory cells. The 3D nonvolatile memory devices having a line type channel layer are advantageous in terms of the degree of integration since only a single-layered select gate is necessary.
FIG. 1 a schematic view illustrating a configuration of a conventional 3D nonvolatile memory device. FIG. 1 illustrates a connection relationship between word lines of cell regions and pass transistors.
Each of cell regions Cell1 and Cell 2 has a 3D structure in which word lines WL are vertically stacked. Pass transistors Pass Tr of an X-decoder, which supply programming voltages to the word lines WL of the cell regions Cell1 and Cell2, are formed in a pass transistor region between the cell regions Cell1 and Cell2. The word lines WL of the cell regions Cell1 and Cell2 are coupled to the pass transistors Pass Tr through local word lines LWL and receive the programming voltages from the pass transistors Pass Tr.
End portions of the word lines WL between the cell regions Cell1 and Cell 2 and the pass transistor region are etched in a stepped type to form a slim region. The slim region is coupled to the local word lines LWL through contacts.
Gates of the pass transistors Pass Tr are coupled to a block word line BLKWL to which a block selection signal is applied. The pass transistors Pass Tr couple the global word lines GWL and the local word lines LWL according to the block selection signal. That is, the pass transistors Pass Tr transfer programming voltages received from the global word lines GWL to the word lines WL of the cell regions Cell1 and Cell2 through the local word lines LWL according to the block selection signal.
In conventional 3D nonvolatile memory devices, the local word lines LWL for coupling the word lines WL and the pass transistors Pass Tr are necessary. However, since the word lines WL are formed in a stacking structure, it becomes difficult to form a large number of metal interconnections LWL in a limited space such as, the pass transistor region. That is, the number of metal interconnections LWL for coupling the word lines WL and the pass transistors Pass Tr increases in proportion to an increase of the number of layers of the word lines. However, since a pitch of the cell block is not increased, a difficulty level for forming the metal interconnections increases.
In particular, it is difficult to ensure sufficient area for the pass transistor region in which one pass transistor Pass Tr is commonly coupled to the word lines of the cell regions Cell1 and Cell2 at both sides thereof.